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ds073 (v1.0) july 26, 2000 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? one-time programmable (otp) read-only memory designed to store configuration bitstreams of xilinx fpga devices simple interface to the fpga; configurable to use a one user i/o pin cascadable for storing longer or multiple bitstreams programmable reset polarity (active high or active low) for compatibility with different fpga solutions supports fast configuration low-power cmos floating gate process 3.3v supply voltage available in compact plastic packages: vq44, pc44, pc20, vo8, and so20 programming support by leading programmer manufacturers. design support using the xilinx alliance and foundation series software packages. dual configuration modes for the xc17v16 and xc17v08 - serial slow/fast configuration (up to 33 mhz) - parallel (up to 264 mhz) guaranteed 20 year life data retention description xilinx introduces the high-density xc17v00 family of config- uration proms which provide an easy-to-use, cost-effec- tive method for storing large xilinx fpga configuration bitstreams. initial devices in the 3.3v family are available in 16 mb, 8 mb, 4 mb, 2 mb, and 1 mb densities. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the fpga din pin. the fpga generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when the fpga is in slave serial mode, the prom and the fpga must both be clocked by an incoming signal. when the fpga is in selectmap mode, an external oscilla- tor will generate the configuration clock that drives the prom and the fpga. after the rising cclk edge, data are available on the proms data (d0-d7) pins. the data will be clocked into the fpga on the following rising edge of the cclk. selectmap does not utilize a length count, so a free-running oscillator may be used. see figure 3 . multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family. for device programming, either the xilinx alliance or foun- dation series development system compiles the fpga design file into a standard hex format, which is then trans- ferred to most commercial prom programmers. 0 xc17v00 series configuration prom ds073 (v1.0) july 26, 2000 08 advance product specification r
xc17v00 series configuration prom 2 www.xilinx.com ds073 (v1.0) july 26, 2000 1-800-255-7778 advance product specification r figure 1: simplified block diagram for xc17v04, xc17v02, and xc17v01 (does not show programming circuit) figure 2: simplified block diagram for xc17v16 and xc17v08 (does not show programming circuit) eprom cell matrix address counter ce data oe output clk v cc v pp gnd ds073_01_072600 tc oe reset/ oe/ reset or ceo eprom cell matrix address counter ce d0 data (serial or parallel mode) oe 8 output clk busy v cc v pp gnd ds073_02_072600 tc oe reset/ oe/ reset or d[1:7] (selectmap interface) ceo 7 7
xc17v00 series configuration prom ds073 (v1.0) july 26, 2000 www.xilinx.com 3 advance product specification 1-800-255-7778 r pin description data[0:7] data output is in a high-impedance state when either ce or oe are inactive. during programming, the d0 pin is i/o. note that oe can be programmed to be either active high or active low. note: xc17v04, xc17v02, and xc17v01 have serial output only. clk each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/oe when high, this input holds the address counter reset and puts the data output in a high-impedance state. the polar- ity of this input pin is programmable as either reset/oe or oe/reset . to avoid confusion, this document describes the pin as reset/oe , although the opposite polarity is pos- sible on all devices. when reset is active, the address counter is held at "0", and puts the data output in a high-impedance state. the polarity of this input is program- mable. the default is active high reset, but the preferred option is active low reset , because it can be driven by the fpgas init pin. the polarity of this pin is controlled in the programmer inter- face. this input pin is easily inverted using the xilinx hw-130 programmer. third-party programmers have differ- ent methods to invert this pin. ce when high, this pin disables the internal address counter, puts the data output in a high-impedance state, and forces the device into low-i cc standby mode. ceo chip enable output, to be connected to the ce input of the next prom in the daisy chain. this output is low when the ce and oe inputs are both active and the internal address counter has been incremented beyond its terminal count (tc) value. in other words: when the prom has been read, ceo will follow ce as long as oe is active. when oe goes inactive, ceo stays high until the prom is reset. note that oe can be programmed to be either active high or active low. busy (xc17v16 and xc17v08 only) if busy pin is floating, the user must program the busy bit which will cause busy pin to go low internally. when asserted high, output data are held and when busy pin goes low, data output will resume. v pp programming voltage. no overshoot above the specified max voltage is permitted on this pin. for normal read oper- ation, this pin must be connected to v cc . failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. do not leave v pp floating! v cc and gnd positive supply and ground pins. prom pinouts for xc17v16 and xc17v08 capacity pin name 44-pin vqfp 44-pin plcc busy 24 30 d0 40 2 d1 29 35 d2 42 4 d3 27 33 d4 9 15 d5 25 31 d6 14 20 d7 19 25 clk 43 5 reset/oe (oe/reset ) 13 19 ce 15 21 gnd 6, 18, 28, 27, 41 3, 12, 24, 34, 43 ceo 21 27 v pp 35 41 v cc 8, 16, 17, 26, 36, 38 14, 22, 23, 32, 42, 44 devices configuration bits xc17v16 16,777,216 xc17v08 8,388,608
xc17v00 series configuration prom 4 www.xilinx.com ds073 (v1.0) july 26, 2000 1-800-255-7778 advance product specification r prom pinouts for xc17v04, xc17v02, and xc17v01 capacity controlling proms connecting the fpga device with the prom. the data output(s) of the of the prom(s) drives the d in input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s). the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the reset /oe input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. other methods ? such as driving reset /oe from ldc or system reset ? assume the prom internal power-on-reset is always in step with the fpga ? s internal power-on-reset. this may not be a safe assumption. the prom ce input can be driven from either the ldc or done pins. using ldc avoids potential contention on the d in pin. the ce input of the lead (or only) prom is driven by the done output of the lead fpga device, provided that done is not permanently grounded. otherwise, ldc can be used to drive ce , but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. selectmap mode is similar to slave serial mode. the data is clocked out of the prom one byte per cclk instead of one bit per cclk cycle. see fpga data sheets for special configuration requirements. pin name 8-pin voic 20-pin soic 20-pin plcc 44-pin vqfp 44-pin plcc data 112402 clk 2 3 4 43 5 reset/oe (oe/reset ) 38 6 1319 ce 410 8 15 21 gnd 5 11 10 18, 41 24, 3 ceo 61314 21 27 v pp 71817 35 41 v cc 82020 38 44 devices configuration bits xc17v04 4,194,304 x c 17 v 02 2 , 70 1 , 31 2 xc17v01 1,679,360 xilinx fpgas and compatible proms device configuration bits prom XCV50 559,200 xc17v01 xcv100 781,216 xc17v01 xcv150 1,040,096 xc17v01 xcv200 1,335,840 xc17v01 xcv300 1,751,808 xc17v02 x c v 400 2 , 546 , 048 x c 17 v 0 2 x c v 600 3 , 607 , 968 x c 17 v 04 x c v 800 4 , 715 , 616 x c 17 v 08 xcv1000 6,127,744 xc17v08 XCV50e 630,048 xc17v01 xcv100e 863,840 xc17v01 xcv200e 1,442,106 xc17v01 xcv300e 1,875,648 xc17v02 x c v 400e 2 , 693 , 440 x c 17 v 0 2 xcv405e 3,340,400 xc17v04 xcv600e 3,961,632 xc17v04 xcv812e 6,519,648 xc17v08 xcv1000e 6,587,520 xc17v08 xcv1600e 8,308,992 xc17v08 xcv2000e 10,159,648 xc17v16 xcv2600e 12,922,336 xc17v16 xcv3200e 16,283,712 xc17v16 notes: 1. the suggested prom is determined by compatibility with the higher configuration frequency of the xilinx fpga cclk. xilinx fpgas and compatible proms device configuration bits prom
xc17v00 series configuration prom ds073 (v1.0) july 26, 2000 www.xilinx.com 5 advance product specification 1-800-255-7778 r fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are estab- lished by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the con- figuration program from an external memory. the xilinx proms have been designed for compatibility with the mas- ter serial mode. upon power-up or reconfiguration, an fpga enters the master serial mode whenever all three of the fpga mode-select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. syn- chronization is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration inter- face. only a serial data line and two control lines are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function din pin on the fpga is used only for configuration, it must still be held at a defined level during normal operation. the xilinx fpga families take care of this automatically with an on-chip default pull-up resistor. programming the fpga with counters unchanged upon completion when multiple fpga-configurations for a single fpga are stored in a prom, the oe pin should be tied low. upon power-up, the internal address counters are reset and con- figuration begins with the first program stored in memory. since the oe pin is held low, the address counters are left unchanged after configuration is complete. therefore, to reprogram the fpga with another program, the done line is pulled low and configuration begins at the last value of the address counters. this method fails if a user applies reset during the fpga configuration process. the fpga aborts the configuration and then restarts a new configuration, as intended, but the prom does not reset its address counter, since it never saw a high level on its oe input. the new configuration, therefore, reads the remaining data in the prom and inter- prets it as preamble, length count etc. since the fpga is the master, it issues the necessary number of cclk pulses, up to 16 million (2 24 ) and done goes high. however, the fpga configuration will be completely wrong, with potential contentions inside the fpga and on its output pins. this method must, therefore, never be used when there is any chance of external reset during configuration. cascading configuration proms for multiple fpgas configured as a daisy-chain, or for future fpgas requiring larger configuration memories, cas- caded proms provide additional memory. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and disables its data line. the second prom recognizes the low level on its ce input and enables its data output. see figure 3 . after configuration is complete, the address counters of all cascaded proms are reset if the fpga r eset pin goes low, assuming the prom reset polarity option has been inverted. to reprogram the fpga with another program, the done line goes low and configuration begins where the address counters had stopped. in this case, avoid contention between data and the configured i/o use of din.
xc17v00 series configuration prom 6 www.xilinx.com ds073 (v1.0) july 26, 2000 1-800-255-7778 advance product specification r figure 3: (a) master serial mode (b) virtex selectmap mode (dotted lines indicates optional connection) program din cclk init done first prom data ceo busy busy clk ce optional slave fpgas with identical configurations vcc fpga (low resets the address pointer) v cc v cco optional daisy-chained fpgas with different configurations oe/reset dout modes* vcco virtex select map busy busy cs write init d[0:7] cclk done clk virtex select map mode, xc17v16 and xc17v08 only. d[0:7] ce oe/reset xc17vxx modes*** 3.3v external osc ceo 4.7k v cc 4.7k v cc ** ** v cc v cco v cc v cco v cc 1k i/o* master serial mode 8 i/o* 1k *cs and write must be pulled down to be used as i/o. one option is shown. **virtex, virtex-e is 300 ohms, all others are 4.7k. ***for mode pin connections, refer to the appropriate fpga data sheet. ds073_03_072600 *for mode pin connections, refer to the appropriate fpga data sheet. **virtex, virtex-e is 300 ohms, all others are 4.7k. cascaded prom data clk ce oe/reset
xc17v00 series configuration prom ds073 (v1.0) july 26, 2000 www.xilinx.com 7 advance product specification 1-800-255-7778 r standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high imped- ance state regardless of the state of the oe input. programming the devices can be programmed on programmers supplied by xilinx or qualified third-party vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. table 1: truth table for xc17v00 control inputs control inputs internal address outputs reset ce data ceo i cc inactive low if address < tc (1) : increment if address > tc (1) : don ? t change active high-z high low active reduced active low held reset high-z high active inactive high not changing high-z high standby active high held reset high-z high standby notes: 1. the xc17v00 reset input has programmable polarity 1. tc = terminal count = highest address value. tc + 1 = address 0.
xc17v00 series configuration prom 8 www.xilinx.com ds073 (v1.0) july 26, 2000 1-800-255-7778 advance product specification r absolute maximum ratings operating conditions (3v supply) dc characteristics over operating condition symbol description conditions units v cc supply voltage relative to gnd ? 0.5 to +7.0 v v pp supply voltage relative to gnd ? 0.5 to +12.5 v v in input voltage relative to gnd ? 0.5 to v cc +0.5 v v ts voltage applied to high-z output ? 0.5 to v cc +0.5 v t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temperature (10s @ 1/16 in.) +260 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc (1) supply voltage relative to gnd (t a = 0 c to +70 c) commercial 3.0 3.6 v supply voltage relative to gnd (t a = ? 40 c to +85 c) industrial 3.0 3.6 v notes: 1. during normal read operation v pp must be connect to v cc. symbol description min max units v ih high-level input voltage 2 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ? 3 ma) 2.4 - v v ol low-level output voltage (i ol = +3 ma) - 0.4 v i cca supply current, standby mode (at maximum frequency) (xc17v16 and xc17v08 only) - 100 ma i ccs supply current, standby mode ( xc17v16, xc17v08, xc17v04, xc17v02 only) - 350 a i cca supply current, standby mode (at maximum frequency) (xc17v04, xc17v02, and xc17v01 only) -10ma i ccs supply current, standby mode ( xc17v01 only) -50 a i l input or output leakage current ? 10 10 a c in input capacitance (v in = gnd, f = 1.0 mhz) - 10 pf c out output capacitance (v in = gnd, f = 1.0 mhz) - 10 pf
xc17v00 series configuration prom ds073 (v1.0) july 26, 2000 www.xilinx.com 9 advance product specification 1-800-255-7778 r ac characteristics over operating condition for xc17v04, xc17v02, and xc17v01 symbol description min max units t oe oe to data delay - 30 ns t ce ce to data delay - 45 ns t cac clk to data delay - 45 ns t df ce or oe to data float delay (2,3) -50ns t oh data hold from ce , oe , or clk (3) 0-ns t cyc clock periods 67 - ns t lc clk low time (3) 25 - ns t hc clk high time (3) 25 - ns t sce ce setup time to clk (to guarantee proper counting) 25 - ns t hce ce hold time to clk (to guarantee proper counting) 0 - ns t hoe oe hold time (guarantees counters are reset) 25 - ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds073_04_072600 t cyc
xc17v00 series configuration prom 10 www.xilinx.com ds073 (v1.0) july 26, 2000 1-800-255-7778 advance product specification r ac characteristics over operating condition for xc17v16 and xc17v08 symbol description min max units t oe oe to data delay - 15 ns t ce ce to data delay - 20 ns t cac clk to data delay (2) -20ns t df ce or oe to data float delay (3,4) -35ns t oh data hold from ce , oe , or clk (4) 0-ns t cyc clock periods 67 - ns t lc clk low time (4) 25 - ns t hc clk high time (4) 25 - ns t sce ce setup time to clk (to guarantee proper counting) 25 - ns t hce ce hold time to clk (to guarantee proper counting) 0 - ns t hoe oe hold time (guarantees counters are reset) 25 - ns t sbusy busy setup time 5 - ns t hbusy busy hold time 5 - ns t wku v cc reached normal supply voltage range to output valid 100 - ms notes: 1. ac test load = 50 pf. 2. when busy = 0. 3. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 4. guaranteed by design, not tested. 5. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. reset/oe ce clk busy data t ce t oe t lc t sce t sce t hce t hoe t cac t sbusy t hbusy t oh t df t oh t hc ds073_05_072600 t cyc
xc17v00 series configuration prom ds073 (v1.0) july 26, 2000 www.xilinx.com 11 advance product specification 1-800-255-7778 r ac characteristics over operating condition when cascading symbol description min max units t cdf clk to data float delay (2,3) -50 ns t ock clk to ceo delay (3) -30 ns t oce ce to ceo delay (3) -35 ns t ooe reset/oe to ceo delay (3) -30 ns notes: 1. ac test load = 50 pf 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. reset/oe clk data ce t ooe ceo first bit last bit t oce t ock t cdf ds073_06_062800 t oce
xc17v00 series configuration prom 12 www.xilinx.com ds073 (v1.0) july 26, 2000 1-800-255-7778 advance product specification r ordering information valid ordering combinations marking information due to the small size of the commercial serial prom packages, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows: revision history the following table shows the revision history for this document. xc17v16vq44c xc17v08vq44c xc17v04pc20c xc17v02pc20c xc17v01pc20c xc17v16pc44c xc17v08pc44c xc17v04pc44c xc17v02pc44c xc17v01vo8c xc17v16vq44i xc17v08vq44i xc17v04vq44c xc17v02vq44c xc17v01so20c xc17v16pc44i xc17v08pc44i xc17v04pc20i xc17v02pc20i xc17v01pc20i xc17v04pc44i xc17v02pc44i xc17v01vo8i xc17v04vq44i xc17v02vq44i xc17v01so20i xc17v16 pc44 c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = ? 40 to +85 c) package type vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier v08 = 8-pin plastic small outline thin package pc20 = 20-pin plastic leaded chip carrier so20 = 20-pin plastic small outline package device number xc17v16 xc17v08 xc17v04 xc17v02 xc17v01 17 v 16 p c 44 c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = ? 40 to +85 c) package type vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier v08 = 8-pin plastic small outline thin package pc20 = 20-pin plastic leaded chip carrier so20 = 20-pin plastic small outline package device number 17 v 16 17 v 08 17 v 04 17 v 02 17 v 01 date version revision 07/26/00 1.0 initial xilinx release.

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